Welcome to the MedLibrary.org Wikipedia Supplement on Wafer (electronics) -- Please Click to Return to Front Page

An etched silicon wafer

Intel's silicon wafer

A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuit and other microdevices. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning.

Several types of solar cells are made from such wafers. A solar wafer is a circular solar cell made from the entire wafer (rather than cutting into smaller rectangular solar cells).

Formation

See also: Ingot

The Czochralski process.

2 inch, 4 inch, 6 inch, and 8 inch wafers

Wafers are formed of highly pure (99.9999% purity), ¹ nearly defect-free single crystalline material². One process for forming crystalline wafers is known as Czochralski growth invented by the Polish chemist Jan Czochralski. In this process, a cylindrical ingot of high purity crystalline silicon is formed by pulling a seed crystal from a 'melt'. ^{3 4}

The ingot is then sliced with an inner diameter diamond coated blade and polished to form wafers ⁵. The size of wafers is 100 – 200 mm square and the thickness is 200 -300 μ. In the future, 160 μ will be the standard ⁶.

The resulting thin wafers can then be doped to achieve the desired electronic properties.

Cleaning, texturing and etching

Wafers are cleaned with weak acids to remove unnecessary particles, or repair damage caused in the sawing process. The wafers are textured to create a rough surface to increase the solar cell efficiency. The generated PSG (Phosphorous Silicate Glass) is removed from the edge of the wafer in the etching ⁷.

Wafer properties

Standard wafer sizes

Silicon wafers are available in a variety of sizes from 1 inch (25.4 mm) to 300 mm (11.8 inches). ⁸ Semiconductor fabrication plants (also known as fabs) are defined by the size of wafers that they are tooled to produce. The size has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab considered to be 300mm (12 inch), with the next standard set to be 450mm (18 inch).⁹¹⁰ Intel, TSMC and Samsung are separately conducting research to the advent of 450mm "prototype" (research) fabs by 2012. Dean Freeman, an analyst with Gartner Inc., predicted that production fabs could emerge sometime between the 2017 and 2019 timeframe.¹¹

• 1 inch.
• 2 inch (50.8 mm). Thickness 275 µm.
• 3 inch (76.2 mm). Thickness 375 µm.
• 4 inch (100 mm). Thickness 525 µm.
• 5 inch (127 mm) or 125 mm (4.9 inch). Thickness 625 µm.
• 150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
• 200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
• 300 mm (11.8 inch, usually referred to as "12 inch" or "Pizza size" wafer). Thickness 775 µm.
• 450 mm ("18 inch"). Thickness 925 µm (expected).¹²

Wafers grown using materials other than silicon are generally not available in sizes over 100 mm, and will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling.

Analytical die count estimation

For any given wafer diameter d, mm and target IC size S, mm², there is an exact number of integral die pieces that can be sliced out of the wafer. The gross Die Per Wafer DPW can be estimated by the following expression:

Note, that the gross die count does not take into account the die defect loss, various alignment markings and test sites on the wafer.

Crystalline orientation

Diamond Cubic Crystal Structure, Silicon unit cell

Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed.

Wafers are grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm). ¹³ When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with [100] or [111] faces being the most common for silicon. ¹³ Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer's crystal orientation, since each direction offers distinct paths for transport. ¹⁴ Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.

Wafer flats and orientation notches

Wafers under 200 mm generally have flats cut into one or more sides indicating crystallographic planes of high symmetry (usually the {110} face) and, in old-fashioned wafers (those below about 100 mm diameter), the wafer's orientation and doping type (see illustration for conventions). Modern wafers use a notch to convey this information, in order to waste less material ¹⁵.

Impurity doping

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 10¹³ and 10¹⁶ per cm³ of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type.¹⁶ However, compared with single-crystal silicon's atomic density of 5×10²² atoms per cm³, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum. ¹⁷ Transition metals, in particular, must be kept below parts per billion concentrations for electronic applications. ¹⁸

Compound semiconductors

While silicon is the most prevalent type of wafer used in the electronics industry, other compound III-V or II-VI type wafers have also been employed. Gallium arsenide (GaAs) wafers are one common III-V semiconductor material which can be produced using the Czochralski process. ⁴

See also

• Crystalline silicon
• Epilayer
• Epitaxy
• Junction
• Layer (electronics)
• Low-cost solar cell
• Rapid thermal processing
• Refining
• Screen printing
• Silicon on insulator (SOI) wafers
• Solar panel
• RCA clean
• Zone melting

References

External links

Wikimedia Commons has media related to: Wafers

• Everything Wafers - A guide to semiconductor substrates type, property, cleaving, etching, and fabrication.
• Star Silicon - Information and products related to the Silicon Wafer and Solar Wafer industry.

Wikipedia content modification information:

• This page was last modified on 26 November 2008, at 11:28.

Wikipedia Authorship and Review

Wikipedia content provided here is not reviewed directly by MedLibrary.org. Wikipedia content is authored by an open community of volunteers and is not produced by or in any way affiliated with MedLibrary.org.

Wikipedia Usage Guidelines

This article is licensed under the GNU Free Documentation License. It uses material from the Wikipedia article on "Wafer (electronics)".

The URL for this specific entry is:

• http://medlibrary.org/medwiki/Wafer_(electronics)

All Wikipedia text is available under the terms of the GNU Free Documentation License. (See Copyrights for details). Wikipedia® is a registered trademark of the Wikimedia Foundation, Inc.